| 摘要 |
<p>An on-chip memory control circuit generates a proper WRITE STROBE signal for a clock synchronized pipe-line operated integrated circuit memory. A symmetrical clock signal having half the frequency of the system clock is produced by applying the system clock to the C input of a standard master slave delay type flip-flop (2) having its Q output fed back to its D input. A negative going pulse train O/p comprising a pulse at every transition of the symmetrical clock is generated by a level change detector (4-24) which issues a pulse of a desired width whenever a level change at its input is detected. A delayed pulse train O/PD is produced at a delay (26) delaying phip an amount which depends on the speed of the memory and other design criteria. The pulse trains O/p and O/PD are applied to an asynchronous flip-flop (30), the output of which corresponds to the desired WRITE STROBE signal. </p> |
