发明名称 DIGITAL SIGNAL DETECTOR
摘要 PURPOSE:To control plural devices with simple constitution by using a D type FF to superpose serial data and a digital signal to be detected. CONSTITUTION:A D type FF401 containing set and reset terminals is provided together with AND circuits 402 and 403. The output of the circuit 402 is connected to the set terminal of the FF401, and at the same time the output of the circuit 403 is connected to the reset terminal R of the FF401. While the timing pulse ST is applied to the input terminal of the other side of the circuits 402 and 403 respectively. Then the digital signal J to be detected is applied to the other input terminal of the circuit 402, and the signal J is supplied to the other input terminal of the circuit 403 via an inverter 404. Thus the data signal to be applied to the FF401 is superposed on the digital signal to be detected synchronously with the timing pulse to obtain a serial signal Q. This signal Q is delivered.
申请公布号 JPS59133727(A) 申请公布日期 1984.08.01
申请号 JP19830008467 申请日期 1983.01.20
申请人 MATSUSHITA DENKI SANGYO KK 发明人 KUSABA RIYUUICHI
分类号 H03K5/00;H03K5/135;H03K5/153;H03K5/19;(IPC1-7):H03K5/153 主分类号 H03K5/00
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