| 摘要 |
PURPOSE:To make a processing means possible to input or output plural n-bit parallel data, by providing a gate switching means which supplies control signals successively and outputting one control signal from the processing means. CONSTITUTION:When an input request signal is given from a processor 5 to a switching part 14, the first port signal is outputted to a first-in first-out memory FIFO1 and a gate 3 from the switching part 14 through a signal line 15. At this time, the second port signal is not outputted to a signal line 16. The gate 3 is opened by the first port signal, and 8-bit parallel data is inputted to the processor 5 from the FIFO1 through busses 12a and 13. After a preliminarily determined time from said reception of the input requst signal, the second port signal outputted from the switching part 14 is given to an 8-bit FIFO memory 2 and a gate 4. The gate 4 is opened to input 8-bit parallel data from the FIFO2 to the processor 5, and thus the input of 16-bit data is completed. |
