发明名称 PLL SYNTHESIZER SYSTEM
摘要 PURPOSE:To reduce the phase noise by dividing the desired frequency range of a voltage controlled oscillator VCO to secure the variation in a narrow range. CONSTITUTION:A VCO1 switched and actuates plural VOCs narrower in the frequency range than that of VCO1 by selection control voltages 13<1>-13<n> or actuates by switching a variable constant of an LC tuning circuit of the VCO1. A programmable frequency divider 2 supplies the frequency setting data to a program terminal from a frequency control part 6. The output of the program terminal is compared with the reference frequency fR in terms of phase through a phase wave detector 3. Then the phase difference detection voltage E11 is applied to the VCO1 through an LPF4. The part 6 sends the frequency data to the divider 2 and at the same time switches the intermitting bands of the band selection control voltage between upper and lower limits of the frequency data. In addition, the control voltage E12 of an external circuit can cover consecutively the entire band regardless of the division of band of the VCO1 by changing the voltage E11 through a level shifting circuit 5.
申请公布号 JPS59133738(A) 申请公布日期 1984.08.01
申请号 JP19830007570 申请日期 1983.01.20
申请人 YAESU MUSEN KK 发明人 FUJIKI SHIROU
分类号 H04B1/26;H03L7/187 主分类号 H04B1/26
代理机构 代理人
主权项
地址