发明名称 BIAS GENERATING CIRCUIT
摘要 PURPOSE:To eliminate operation defects at a start time, by providing a starting circuit, which consists of a diode-connected N-channel MISFET, for the purpose of securing the operation at the power-on time of a bias circuit. CONSTITUTION:For the purpose of securing the operation at the power-on time of the bias circuit consisting of MISFETs T1-T5, the starting circuit consisting of a diode-connected N-channel MISFETT6 is provided. If the potential of a node N2 does not rise to enough value to make the FETT1 conductive though the power source is turned on, the voltage detecting means T6 is made conductive in accordance with this potential to raise the potential of the node N2. Thus, if enough capacity divided voltage to make the FETT1 conductive appears in the node N2 though the capacity divided voltage appearing between gates and sources of FETs T4 and T5 is lower than a threshold voltage, a bias current is given to the FETT4 by the FETT1 which is made conductive. Consequently, the circuit consisting of FETs T1-T5 enters into the operating state.
申请公布号 JPS59133618(A) 申请公布日期 1984.08.01
申请号 JP19830007234 申请日期 1983.01.21
申请人 HITACHI SEISAKUSHO KK 发明人 SAKAGUCHI JIROU
分类号 G05F3/24;G05F3/26 主分类号 G05F3/24
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