| 摘要 |
A frequency synthesizer having a delay line for a controlling element. The output frequency of a voltage controlled oscillator (VCO) is sampled with a directional coupler and input to an in-phase power divider. The first output of the power divider is input to a delay line to provide a delayed signal. The delayed signal and the non-delayed signal from the second output of the power divider are input to a phase detector. The output of the phase detector is a DC voltage representative of the phase difference between the delayed signal and the non-delayed signal. An analog gate inputs the phase detector output to an oscillator driver that controls the VCO. When the phase difference deviates from a predetermined level the oscillator driver outputs an error voltage to adjust the VCO until the proper phase difference is achieved which will be a condition of phase lock wherein the output frequency is phase locked to the delay line. The predetermined phase difference is determined by the delay of the delay line and the characteristics of the phase detector. A digital-to-analog converter also controls the oscillator driver providing a coarse tuning control for entering new frequency data. A strobe signal will open the analog gate, thus disconnecting the phase detector, when new frequency data is input. When the analog gate is closed the frequency synthesizer will again seek a phase lock condition.
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