| 摘要 |
PURPOSE:To enable to extend the operating voltage extent of a semiconductor device by a method wherein resistance of a well layer containing a buried layer is reduced without changing surface concentration of the well layer. CONSTITUTION:A P type buried diffusion region 22 is formed in an N type substrate 1, and an N type vapor phase growth layer 21 is laminated on the surface side thereof. Then P type well diffusion 2 is performed from the surface of the vapor phase growth layer 21 till exudation of the diffusion region 22 to the layer 21 is connected completely. A P-channel type transistor 3 is formed in the layer 21 manufactured in such a way, and an N-channel type transistor 4 is manufactured in the P-well layer 2. Accordingly, resistance of the P-well layer 2 can be made extremely small according to the buried layer 22 of high concentration, a voltage between the base and the emitter of a parasitic bipolar transistor having a source as an emitter, the well layer 2 as a base, and a drain 8 as a collector can be made small, and starting of parasitic bipolar action can be suppressed, and the working voltage can be enhanced against generation of an impact ion current attendant on curtailment of channel length L. |
