| 摘要 |
<p>PURPOSE:To prevent a voltage mode changing the storage content of a memory cell not erased from being given to a memory cell at partial erase of a memory by controlling a sequence of a voltage given to each terminal of nonselecting memory cell. CONSTITUTION:In figure, 90 is the entire board of a memory IC and 94 is a memory cell itself. A terminal 91 is connected to the board and coupled electrically to the board of transistors (TRs) of the entire substrate. A board voltage Vp is given by turning on a switch 21 to a terminal 22 of which the voltage Vp is given. A signal line 93 is connected to sources of longitudinal TRs, a terminal 95 is connected to a switch 45 and a voltage Vwd is given to a terminal 6. A sensor 53 is connected to the other terminal 96 of the signal line 93. A signal line 31 is connected to gates of a lateral TRs and one terminal 98 is connected to a switch 14. The voltage Vp is given to a terminal 15 at non-erasing state and 0V is given at erasing state.</p> |
