| 摘要 |
PURPOSE:To enable high speed actions and reduce the consumed power by a method wherein a well region formed necessarily on the substrate of a complementary MOS type integrated circuit is divided, and the device is arranged on on this region by selecting the propriety of impressing a high reverse directional voltage. CONSTITUTION:A plurality of P-channel type MOS transistors TrP's are formed on the substrate 1, and P type well regions 2 and 3 alienated from each other are formed on the substrate 1. A plurality of N-channel type MOS transistors TrN1 and TrN2 are formed on these region 2 and 3 respectively; an MOS element such as a memory cell to which a high reverse directional voltage is not impressed is formed on the region 2, and an MOS element to which the high reverse directional voltage is desired to be impressed is formed on the region 3. Then, one power source voltage VDD used in a main complimentary memory circuit is impressed on the substrate 1, the other power source voltage VSS on the well region 2, and a high power source voltage Vsub higher in the negative direction than the voltage VSS on the well region 3. Such a constitution enables to cause the memory cell of the well region 2 to well perform information memory, and to contrive to speed up the action because the junction capacitance becomes small. |
