| 摘要 |
In order to refresh a signal node 41 to true logic level the voltage on that node and on a complementary node 42 control transistors Q41 and Q42, in a control circuit connected between VDD and ground. Accordingly, when node 41 is high level, a control node between the transistors approaches high level. A refresh signal O is applied through a capacitor C43F to the node 43 to turn a transistor switch Q43 hard on and thereby refresh node 41 to VDD. Another embodiment comprises an inverter whose input and output provide complementary and true signals corresponding to those on the nodes 41 and 42. In another embodiment, the circuit is duplicated for the two signal nodes which are cross-coupled by a flip-flop circuit. The control nodes are also cross-coupled by a flip-flop circuit. The circuit overcomes problems in known refresh system for dynamic random access memories. |
