| 摘要 |
PURPOSE:To suppress the deterioration in accessing performance by discriminating a bit location where an error exists and correcting the error of a data section. CONSTITUTION:All bits except the least significant bit at an address corresponding to an RAM/ROM 12 are accessed by the output of a selector 10. Then, a parity check circuit 27, a syndrome decoder 28, and a discriminating logical circuit 30 discriminate whether a bit having an error of the RAM/ROM 12 having a data section and an ECC section in one word exists in the data section or the ECC section. Further, a data section error correcting circuit 29 is provided so as to correct the error only when the error exists in the data section so as to omit the time correcting the error of the ECC section in one word of the storage device. |
