| 摘要 |
PURPOSE:To obtain a double comparison speed as high as a single comparator by connecting two comparator circuits in parallel to form one comparator and operating a clock signal of an analog switch of one comparator circuit and that of an analog switch of the other comparator circuit in opposite phases. CONSTITUTION:The comparators A, B are operated by a positive and a negative phase of a clock separately. Further, switches 7, 7', 8, 8', 9, 9', 10, 10', electric charge capacitors 11, 11', inverters 12, 12', and latches 13, 13' are provided and analog inputs VIN1 and VIN2 are applied. Contents of the comparator A and contents of the comparator B are outputted alternately in the timing of phi and phi' respectively to an output OUT in the constitution like this. Thus, the double comparison speed is obtained in comparison with the single use of the comparators A, B. |
