SEMICONDUCTOR MEMORY ARRAY

摘要

PHA 1048 13 12-3-1981 "Semiconductor memory array." An improved read-only memory arrangement for generating a differential output signal within the memory array (11) itself incorporates a column of reference cell translators (16) and a single reference bit line (13) within the same general area occupied by the memory cell transistors (10) and memory main bit lines (12). Each word line is coupled to the gate of one of the reference cell transistors (16) as well as to the gates of the memory cell transistors (10) lying in the same row. The reference bit line voltage is maintained substantially midway between the high and low potential levels of the main bit lines to produce a differential output voltage for sensing purposes.