| 摘要 |
<p>D-23,728 ERROR RATE DETECTOR by Robert A. Karchevski One or a burst of error signals from an error detector are applied to one input of a latch. The first error received during a "window" forces the latch to a set position, and a subsequent enabling pulse reads the error occurrence into the count up input of an up-down counter. Following the enable pulse, the latch is reset. If one or more errors occur during the subsequent window period, another error ocurrence is read into the count up input. Otherwise, the occurrence of the enable pulse reads the absence of an error into the down count input of said up-down counter. On a full count, an output latch circuit is set by an output signal from the counter. The latch is not reset until a zero count is obtained in the up-down counter. Overflow and underflow are prohibited by circuits external to the up-down counter.</p> |
