| 摘要 |
PURPOSE:To generate the precharging signal of a transition detector system and the internal address signal of an address buffer system in invariably specific order by setting the threshold values of the 1st, the 2nd, and the 3rd comparators in a specified correlation. CONSTITUTION:The output of the 1st comparator 3 is supplied to one input of an NOR gate 51 directly and to the other input through three inverters 52, 53, and 54 in series. The output of the 2nd comparator 4 is supplied to one input of an NAND gate 57 directly and to the other input through three inverters 58, 59, and 60 in series. Then, the output of the 3rd comparator 6 is supplied to the address buffer system 7 through an inverter 8 to generate an internal address signal AI. Then it is assumed that the precharging signal PC should be supplied to restrict a memory circuit after the internal signal AI is supplied. In this case, the threshold values V1, V2, and V3 of the 1st, the 2nd, and the 3rd comparators 3, 4, and 6 are so set that V2<V3<V1. |
