| 摘要 |
PURPOSE:To accelerate CMOS device by a method wherein field effect transistor with the first and second conductive type source and drain regions are formed respectively in the different conductive type regions on a silicon substrate to be used in a specified temperature range. CONSTITUTION:In a CMOS inverter circuit comprising PMOS Q1 and NMOS Q2, PMOS is formed in p<+> regions 205, 206 and a gate electrode 207 on the surface of an n type silicon substrate 201 while NMOS is formed in n<+> regions 203, 204 in a p type well. This element is used in the temperature range not exceeding 100K e.g. 77K. Through these procedures, CMOS device may be highly integrated and accelerated since NMOS and PMOS may approach to each other. |
