| 摘要 |
PURPOSE:To reduce interruption in the processing of a processor by providing a timer corresponding to a row address and making a request to refresh when the timer clocks a specific time or longer, and clearing the timer corresponding to an address when the access to or refreshing of the address is completed. CONSTITUTION:A timer TIM receives the high-order address signal UA selected by a selector SEL3 or the contents of a scanning counter CNT as an address signal to have a timer area specified, and the reading or writing of the contents of the timer area is performed by a read/write control signal (d). The most significant digit bit of the timer area is used as a refresh-request flag and the most significant digit bit which is read out is applied to a flip-flop circuit FF2. The readout contents are increased by one through a +1 circuit PS and written in the timer area through a selector SEL4 and a flip-flop circuit FF1 at the timing wherein writing is indicated. Further, when the selector SEL4 selects the output of an initial value setting circuit IV, the timer area is initialized at the timing of writing. |
