| 摘要 |
PURPOSE:To form a priority shifting circuit with a small number of elements by providing two FFs which latch DMA request signals and supplying alternately the signals which give the priority while both FFs is latching the DMA request signals. CONSTITUTION:A DMA interval controller 2 is provided to two DMA request signals REQA and REQB together with FF5 and FF6. These FFS latch the outputs of differentiating circuits 3 and 4 which differentiates the DMA time signal DMASTAR of the controller 2. If just a single DMA request signal exists, the FF5 latches the request signal and delivers a priority signal DIR. When both FF5 and 6 latch the DMA request signals, the signals DIR are delivered alternately. Thus it is possible to obtain a priority deciding/shifting circuit with a small number of elements. |
