| 摘要 |
PURPOSE:To speed up arithmetic by allowing a logical decision making part as hardware to decide on a mantissa data part is in an all-''0'' state or not, digit by digit, and detecting a significant bit start position in normalizing and multiplying operation. CONSTITUTION:The output of the logical decision making part consisting of NOR gates 2-0-2-5 and inverters 3-1-3-5 is ''111000'', which is passed through an encoder 4, so that digits to be normalized are ''011''. Those digits are subtracted from exponent part data (N) to find a normalized exponent part (N-3). The digits are made into a counter input ''11110011'' (high-order four digits for a counter 8 and low-order four digits for a counter 9) to generate a shift register control signal, normalizing the mantissa data part. In this case, 12 bits are shifted to left. At this time, digits ''00001100'' is held in a buffer 6. |
