发明名称 MULTI-PROCESSOR SYSTEM
摘要 PURPOSE:To shorten the waiting time due to the bus conflict by giving an access to a shared memory after switching and selecting successively the buses in accordance with the address value. CONSTITUTION:Buses B1-Bn are connected to a shared memory M. The region of the memory M is divided into regions M0-Mn-1, and the buses B1-Bn are connected to these regions respectively. Then CPU blocks CB0-CBn-1 are connected to the buses B1-Bn. These CPU blocks switch and select successively the buses B1-Bn in accordance with the value of the address which gives an access to the memory M.
申请公布号 JPS59125465(A) 申请公布日期 1984.07.19
申请号 JP19820234148 申请日期 1982.12.31
申请人 FUJITSU KK 发明人 KUROKI SHINICHI
分类号 G06F15/16;G06F12/00;G06F15/173;G06F15/177 主分类号 G06F15/16
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