| 摘要 |
PURPOSE:To cope with miniaturization of a memory element, by utilizing the difference in etching rates at a doped part and a nondoped part, and selectively reducing the size of only the channel part of a memory FFET. CONSTITUTION:A field oxide film 6 and a gate oxide film 4 are provided, and floating poly Si 8 is deposited. Poly Si for a control gate is stacked through an insulating film 2. Doping is performed in a region 11 other than a part 10, which is to become a channel. Then photoetching is performed. Since the amount of etching at the side surface of the region 11 is large, the width of the poly Si line becomes small only at the channel part even though the width of a mask line is constant. Thereafter, the insulating films 2 and 4 and the poly Si film 8 are etched in accordance with the sizes of the regions 10 and 11. Therefore, only the channel length of a novolatile element can be shortened. Then, an N<+> layer 5 is formed, and the resistance of a control gate poly Si 1 is reduced. In this constitution, drawbacks in the conventional manufacturing processes are eliminated, and the miniaturization of the element can be handled. |
