| 摘要 |
PURPOSE:To obtain a carry signal generator which generates a carry signal at a high speed with small power consumption and is IC-implemented suitably by simplifying a carry signal transmission line, and transmitting the carry signal while reducing the load capacity. CONSTITUTION:The (i)th-bit valus Ai and Bi of an addend and an augend are ''1'' or ''0''. Then, positive-phase input and output terminals 10 and 11 and negative-phase input and output terminals 12 and 13 are provided. Further, N channel enhancement CMOSs 1-4 operate as switches and CMOSs 5-8 operate as gates. When Ai=Bi=0, only an NOR gate 5 outputs ''1'' and the terminal 11 is at the ground potential, so that a carry output Ci+1=0. When Ai=1 and Bi= 0, only a gate 6 outputs ''1'', and the terminal 11 is connected to the positive- phase carry input terminal, so that Ci+1=Ci and Ci'+1=Ci'. Consequently, a carry signal transfer circuit transfers a logically correct carry signal to the trailing stage. |
