| 摘要 |
PURPOSE:To supply data when access to a main memory is possible and to improve the efficiency of utilization of a data buffer by supplyng a memory request signal and an address to a main memory control part separately from the data. CONSTITUTION:When a vector store instruction is transmitted, the adder 13 of an access pipeline 10 generates the starting address of an element and this is converted by an address conversion part 14 into a real address to the main memory; and this real address is supplied to the main memory control part 11 and stored in an address buffer 15 temporarily. Further, data on four elements from a vector output register VOR24 is stored in a data buffer 25 temporarily. The access control circuit 23 of this control part 11 is provided with a priority control function and a signal DTW for a wait for data transfer is transmitted and received to and from the main memory 12 to send a priority permission signal to the line 10. Then, an aligning circuit 26 reads data out of the buffer 25 in parallel and the data is supplied to the main memory 12 through a data operation part 27 to improve the utilization rate of the buffer 25. |
