发明名称 BUS REQUESTING CIRCUIT
摘要 PURPOSE:To prevent malfunction due to a permission signal for use of an old bus despite the continuous bus requesting for a system containing an arranging device for the competition of bus requests, by adding a simple element to each data processor. CONSTITUTION:Each data processor PU contains an R-SFFd and an AND gate AG in addition to a bus request display FFa. When the FFa is reset, the R-SFFd is also reset to invert its output. Then the output of the gate AG is inverted. Thus the connection is cut between the processor PU and a common bus even under reception of a bus use permitting signal given from a bus request competition arranging device BA. Thus it is possible to prevent a malfunction due to an old bus use permitting signal despite the continuous bus requesting.
申请公布号 JPS59123025(A) 申请公布日期 1984.07.16
申请号 JP19820229223 申请日期 1982.12.29
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KOSHA 发明人 SHIMIZU RIYOUICHI;OKADA KATSUYUKI;TANAKA TOSHIROU
分类号 G06F13/362;G06F13/42 主分类号 G06F13/362
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