| 摘要 |
PURPOSE:To speed up level detection by performing the level detection without using a smoothing circuit which may causes detection time to become longer. CONSTITUTION:The output of a voltage comparator 2 is connected to the reset terminal R of a counting circuit 5, so when the output of the voltage comparator 2 goes up to a level ''H'' before the counter counts up to seven, the output 7 of an NAND gate is held at the level ''H''. Then, a signal to be detected is inputted to an input terminal 1 of the voltage comparator 2 and a reference voltage V from a reference voltage source 3 is set to the crest value V of a detection level point; a reset pulse is inputted at every period of the signal to be detected when the crest value is higher than the reference voltage V and the reset pulse is not inputted when not. Therefore, when the level of the signal to be detected varies from the high state wherein the reset pulse is outputted from the voltage comparator 2 to the low state, and when it varies reversely, the state changes are discriminated within a time of a period less than twice the period of the input signal respectively. |
