| 摘要 |
PURPOSE:To remove a folded component from a signal and to simplify the necessity of an analog pre-filter by connecting plural switched capacitors in parallel to an input stage. CONSTITUTION:The switched capacitors 11-14 connected in parallel to an input terminal 10 are driven by clock signals phi1-phi4 having different phases by a 1/4 period each. The charge accumulated in the capacitors 11, 12 is transferred to an integrating capacitor 6 by a clock signal phi5. The charge accumulated in the capacitors 13, 14 is transferred to a capacitor 6 by a clock signal -phi5. Because the clock signals phi1-phi4 have the 1/4 period of a clock signal phi0 and the frequency of integer times the frequency of clock signals except the multiples of 4 generates attenuation polars, the clock signals phi1-phi4 are kept at the high level. Namely, the connection of switched capacitor filter to the input stage makes it possible to remove components folded to a passing band. |
