发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To expand a memory part up to an address region of a DMA control part regardless of a program control ROM to transfer data at a high speed by using an RAM region at a part where the address overlaps between an ROM and an RAM as a data buffer for DMA transfer. CONSTITUTION:The ROM6 is connected to a CPU1 of a Japanese word processor, and a region 7.1 where the address overlaps between the ROM6 and an RAM is connected to a direct memory access controller 8. At the same time, a region 7.2 at the row side where no overlap exists between the address of the RAM is connected between the CPU1 and the controller 8. Then an access is given by the controller 8 and DMA to a memory part where no direct address is possible owing to the address limitation of the CPU1, and the data is transferred while the CPU1 is working. The memory part is expanded up to the address of the controller 8 regardless of the ROM6 for control of program to attain simultaneous an operation at a high speed.
申请公布号 JPS59121452(A) 申请公布日期 1984.07.13
申请号 JP19820227254 申请日期 1982.12.28
申请人 TOSHIBA KK 发明人 ASAKA FUMIO
分类号 G06F12/00;G06F12/06;G06F13/28 主分类号 G06F12/00
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