| 摘要 |
PURPOSE:To prevent the generation of racing by generating 4-phase clocks synchronized with a reference clock and setting up a period interrupting all transfer gates at the inversion of the transfer gate of an adjacent D latch by said clock. CONSTITUTION:A circuit shown by the figure (a) generates 4-phase clocks phi1- phi4 in accordance with the reference clock. If the reference clock is inverted to ''L'' as shown in the figure (b), the 4-phase clocks are also inverted in the order of phi1, phi2, phi3, and phi4. In a shift register shown in the figure (c), clocks phi1, phi2 are applied to the gates of n- and p-channel MOS-FETs of a transfer gate 9a respectively and clocks phi4, phi3 are applied to the gates of n- and p-channel MOS-FETs of a transfer gate 10a in the same manner. At the time T1, the gate 9a is connected and the gate 10a is disconnected. If the reference clock is inverted at that time, the n-MOS in the gate 9a is interrupted by the inversion of clock phi1 and then the p-MOS in the gate 9a is interrupted by the inversion of the clock phi2, so that all the gates 9a, 10a are disconnected. When the clocks phi3, phi4 are inverted, the gate 9a is disconnected and the gate 10a is connected. |
