| 摘要 |
PURPOSE:To simplify the constitution of a control signal generating circuit and to attain a miniature and light weight structure of a terminal device and to improve maintenance capability, by transmitting a clock signal with the prescribed timing and using the clock signal as a transmission control signal. CONSTITUTION:A data collector 2 is connected to a central editing processor 1 by three lead wires. A clock signal is transmitted to the collector 2 from the processor 1 through the 1st lead wire; a data signal is transmitted to the processor 1 from the collector 2 through the 2nd lead wire; and the 3rd lead wire is used as a common line respectively. The clock signal is transmitted from the processor 1 to monitor the data output fed from the collector 2. The continuing time is monitored for the level of the data signal, and the processor 1 changes its mode. Furthermore, the clock signal sent from the processor 1 is sent to the controller 2. |
