| 摘要 |
Non-volatile JRAM cell having interelectrode non-volatile capacitance which is readable and varies with the electrical charge on elements of the device. To program the nonvolatile capacitance, the address lines (word line and bit line) are biased so that a charge is given to the nonvolatile multidielectric stack between the MIS gate and the JFET source of the cell. For a charge of one polarity, an inversion layer of electrons (for a P-type substrate) is formed on the surface of the JFET source, increasing the capacitance between the MIS gate electrode and the JFET gate electrode. For the opposite polarity, an accumulation layer forms at the JFET source surface, decreasing the interelectrode capacitance. The cell is read by presetting one address line, floating that line, then putting a pulse on the other line while reading the voltage output on the floating line.
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