| 摘要 |
PURPOSE:To simplify a data output circuit and to improve the throughput of a CPU circuit, by allowing a slave-side CPU to perform the data output processing. CONSTITUTION:Data is transferred from a CPU17 which is used as a master control circuit to a slave-side CPU12 by a latch circuit 15 and interruption control signals iR1 and iR2 flowed to interrupt control signal lines 19 and 20 connected between CPUs 17 and 12. The CPU17 outputs the interruption control signal iR1 simultaneously with outputting of data to the latch circuit 15 and reports it to the CPU12 that data is set. The CPU12 is inputted with this data and outputs it to the side of a modulator 18 through a P/S converting circuit 13. Next, the CPU12 outputs the interrupt control signal iR2 to request next data. By repeating this operation, the CPU17 outputs data through the CPU12. |
