| 摘要 |
PURPOSE:To generate a stable clock signal by adding limits to a phase difference signal functioning as an output of a phase comparator by an output of a time window generator to decrease the disturbance in a phase synchronization circuit output by a failed input data signal. CONSTITUTION:The phase comparator 4 detects a phase difference of falling time between an input data signal S6 and a frequency divider output S14 and generates a pulse corresponding to the phase difference. Phase difference signals S7, S8 are inputted to a gate 5 together with a time window signal S15. The gate 5 generates phase difference signals S9, S10 where the phase difference signals S7, S8 exceeding a high-level region of the time window signal S15 are eliminated. A synthesized and a high-frequency component are eliminated from S9, S10 serving as gate outputs by a filter 6 and the result is supplied to a VCM7 as a VCM control voltage. An output S12 of the VCM7 is supplied to a frequency divider 8, where the output is frequency-divided into S13, S14, which are supplied to a time window generator 9 together with the S12. The phase difference signals S7, S8 are limited by generating a time window to the time window signal S15, allowing to set limits to a phase difference signal exceeding the time window by the time window. |
