| 摘要 |
PURPOSE:To remove the DC component after conversion in converting 8-bit information to 12-bit information by forming the latter into such a combination wherein the signal after NRZI modulation consists of positive 6-bit and negative 6-bit among 12-bit and the same level of >=4-bit does not continue and making the 8-bit information correspondent 1 to 1 with the combination of the above- mentioned conditions. CONSTITUTION:The information at an input terminal 1 is transferred by each 8-bit in a shift register SR2 and the information on the 8-bit B1-B8 is supplied to a conversion logic 3. The conversion is performaed in the logic 3 according to the conversion equation I and the information on the converted 12-bit P2-P12 is supplied to the SR4. The clock signal of 3/2 times frequency of the clock of an input signal is further supplied from a terminal 5 and the above-mentioned 12-bit are successively read out. The signal is supplied to a JA-FF6, and the clock signal of the terminal 5 is supplied to an FF6, from which the signal subjected to an NRZI modulation is fetched at an output terminal 7. There is the disadvantage that the decreased component increases with the Galor code but this disadvantage is offset by the absence of the DC component. |
