| 摘要 |
PURPOSE:To allow data processors different in performance to operate by the same program by controlling a step signal control means according to a delay time, and controlling the operation speed of the data processors. CONSTITUTION:A device decision circuit 21 decodes a device identification code transmitted from a device identification code setting circuit 8 and outputs a control signal of one of modes A-D according to the result of decoding. Processing is performed at a maximum speed where a processing speed need not be adjusted in mode A. The processing is performed at a minimum speed in mode D, and at intermediate speeds in modes B and C. A counter default value setting circuit 22 sets initially a numeral for the processing speed adjustment for a counter 23. The counter 23 is set initially to 0 for the mode A, to, for example, 3 for the mode B to 5 for the mode C, and to 7 for the mode D respectively. This set value is varied adequately. |
