发明名称 SPEED SIGNAL DETECTOR
摘要 PURPOSE:To reduce ripple of a speed signal while improving the response with the removal of high frequency components by differentiating and then differentiating and inverting outputs in two phases as input of a double phase type rotary encoder to be converted into four signals to synthesize them trimming near the maximum or the minimum thereof. CONSTITUTION:Outputs of a double phase type rotary encoder are supplied into input terminals 1a and 1b and in the normal rotation, A0 advances by 90 deg. with respect to B0. The outputs are respectively differentiated with differentiation circuits 2 and 3. They are inverted with inversion circuits 4 and 5 and outputs thereof A1, B1 and -A1 and -B1 are supplied to an analog switch 6. Inputs A0 and B0 are added with an addition circuit 7 and the input A0 inverted with an inversion circuit 9 is added to the input B0 with an addition circuit 8. Then, outputs C1 and C2 are converted into a pulse by identifying a code with pulse conversion circuits 10 and 11 and a binary counter 12 has four outputs of S1-S4. The outputs are trimmed and synthesized when each high level comes out to produce an output V1. An output of the analog switch 6 is treated with an LPF 13 to remove high frequency components.
申请公布号 JPS59116551(A) 申请公布日期 1984.07.05
申请号 JP19820225920 申请日期 1982.12.24
申请人 MATSUSHITA DENKI SANGYO KK 发明人 KINOSHITA HISASHI;KAKE SHINOBU
分类号 G01P3/42;G01P3/46;G01P13/04 主分类号 G01P3/42
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