| 摘要 |
PURPOSE:To heighten effect of reduction of the scale of the circuit by constituting the circuit of an input side frequency dividing section, an exclusive OR output section that makes respective output from the first and second 1/2 frequency divider input and an output side frequency dividing section that 1/4 divides output of the exclusive OR output section and sends out a counting completion signal. CONSTITUTION:The edge detecting circuit 10 consists of an input side frequency dividing section 11, an exclusive OR output section 12 and an output side frequency dividing section 13, and receives clock pulse CK and a trigger signal TR in the input side, and sends out a counting completion signal CT when fixed number of edges (for instance five) is counted. The input side frequency dividing section 11 consists of the first 1/2 frequency divider 14 and the second 1/2 frequency divider 15 and the two consist of D-flip-flop. The exclusive OR output section 12 is provided with at least an EXOR gate, and takes exclusive logical sum of respective output of the first and second 1/2 frequency divider 14 and 15. The output side frequency dividing section 13 is made by cascading at least the first 1/2 frequency divider 17 and the second 1/2 frequency divider 18, and forms a 1/4 frequency divider as a whole. |
