发明名称 COMPARATOR CIRCUIT HAVING REDUCED INPUT BIAS CURRENT
摘要 <p>A comparator circuit (40) which includes a differential pair of transistors (12, 14) forming differential inputs of the comparator and a voltage level shift circuit (24, 26) coupled in series connection path with the emitters of the pair of transistors. The voltage level shift circuit includes an additional (26) transistor having its collector-emitter path connected in series between an output of the comparator and the emitter of the first pair of transistors; a first diode coupled in a series- conduction path to the emitter of the second one of the pair of transistors and having an anode connected to the base of the additional transistor; and a second diode (42) coupled between the base and emitter of the additional transistor wherein the effective beta of the additional transistor is reduced to reduce the bias current that would otherwise flow through the first transistor when such transistor is rendered conductive by an applied differential input signal. </p>
申请公布号 WO1984002622(A1) 申请公布日期 1984.07.05
申请号 US1983001658 申请日期 1983.10.24
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