发明名称 MACHINE CHECK INTERRUPTION PROCESSING SYSTEM
摘要 PURPOSE:To secure data processing by converting a machine check interruption code into another data, and placing software in a disabled waiting state. CONSTITUTION:For example, a fault occurs during data processing and a decoder 5 decodes a machine check interruption signal. When it is judged that the result of decoding indicates a state wherein the subsequent operation of hardware can not be secured, a variation indication output 1 is sent out. A machine check interruption code MCIC varying circuit 3 sends out an all-0 signal outputted from an MCIC variation data part 7 instead of the machine check interruption signal. This is sent out to a register 9 through a write part 8 and decoded by the machine check processing routine of a control part 10. This signal, however, can not be decoded because of the all-0 state and the interruption processing of a machine check can not be carried on to enter the disabled waiting state, stopping the check of the data processor.
申请公布号 JPS59116858(A) 申请公布日期 1984.07.05
申请号 JP19820228855 申请日期 1982.12.23
申请人 FUJITSU KK 发明人 MATSUMOTO TOSHIO;KATOU MOTOKAZU
分类号 G06F11/00;G06F11/07 主分类号 G06F11/00
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