| 摘要 |
PURPOSE:To input bits of a shift register newly from an optional bit and to shift them by inputting the respective bits selectively and giving the bits priority. CONSTITUTION:When a signal 1 is inputted to a clock pulse input line ICL and a serial data input line to select the 1st bit by address lines A0-An, a latch circuit 31 latches the current signal contents of a data line ID1. At the same time, a pulse line ICLK1 is connected to an OR gate 72, so whose OR result is ''1'' and a one-bit latch circuit 32 stores the contents of a data input terminal D. Consequently, the contents are logic ''0'' because no signal is inputted to one input terminal ICLK2 of the gate 52, whose OR result of the gate 52 is ''0'' without reference to the contents of a data line ID2. The OR gate 62, therefore, depends upon the OR result of an OR gate 42. The OR gate 42 is forced by a resistance 92 to output ''1'' because no signal is inputted, and its OR result depends upon the input to the other terminal. |
