发明名称 TESTING DEVICE FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To reduce considerably a test time by enabling the test in one output signal comparing period even if the output level of an IC to be measured attains multivalue levels. CONSTITUTION:The output level comparing voltages VOH, VOL which are preliminarily set in accordance with a comparing timing signal D after the start of a test, that is, the outputs of output level selecting circuits 33, 34 are changed over at a high speed, and the output E of the output level selecting circuit is obtd. Said output and the output signal A of an IC to be measured are compared and the level of the output signal id sicriminated. The discrimination is made at every timing by emitting a quality discrimination signal F at each of the changed over levels VOH, VOL, and the result thereof is held by holding circuits 44, 45. If the comparing timing is set by each several point in the entire level of the output signal, the discrimination at all the comparing levels can be made in one output signal comparing period. The test time is thus reduced considerably.
申请公布号 JPS59116065(A) 申请公布日期 1984.07.04
申请号 JP19820232506 申请日期 1982.12.23
申请人 TOSHIBA KK 发明人 ISOTANI KAORU;KAMEDA YASUYOSHI
分类号 G01R31/28;G01R31/316 主分类号 G01R31/28
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