| 摘要 |
PURPOSE:To increase the degree of multiplexing without reducing the cycle time of a storage memory by writing or reading from a central controller to the storage memory at the next cycle coincident with a collating circuit. CONSTITUTION:When the content of a counter CRT14 is ''a'', the content of an address (a) of the storage memory CCM10 is read out via an address selecting circuit(ADSEL)22. When the content of an F12 at the address (a) of the CCM10 represents that a channel is not in use, it is stored in a register FR15 and the content of a CTR, i.e., ''a'' is stored in a latch register LRREG16. The content of the CTR14 obtains again ''a'' after 125mus. Since the content is (a-1) before one cycle, the content of the CTR14 is coincident with a (-1) circuit DEC17. When a control command from the central controller to the CCM10 exists and the next cycle, i.e., the content of the CTR is ''a'', since this cycle is not used by the CCM10, the content of a data register DTREG is transmitted to the CCM10 for write or read to the CCM10. |
