发明名称 Buffer circuit
摘要 A buffer circuit comprises a flip-flop which is receives an external input via a first input circuit and a reference voltage via a second input circuit. Internal complementary outputs are then produced via an output circuit. The flip-flop cooperates with at least one level setting device by way of a second input circuit. The level setting device functions to produce a voltage level to deactivate the second input circuit during activation of the flip-flop.
申请公布号 US4458337(A) 申请公布日期 1984.07.03
申请号 US19820354498 申请日期 1982.03.03
申请人 FUJITSU LIMITED 发明人 TAKEMAE, YOSHIHIRO;NOZAKI, SHIGEKI;MEZAWA, TSUTOMU;KABASHIMA, KATSUHIKO;ENOMOTO, SEIJI
分类号 G11C11/413;G11C11/408;H03K3/356;(IPC1-7):G11C13/00 主分类号 G11C11/413
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