发明名称 PLL OSCILLATION CIRCUIT
摘要 PURPOSE:To stabilize the oscillation frequency of a PLL oscillator by branching the output of a setter which controls frequency divider of a PLL to apply the branched output to an analog oscillator outside the PLL, and switching the output of a PLL reference oscillation to that of an analog oscillator in an unlocked period of the PLL. CONSTITUTION:The oscillation frequency of a VCO1 of a PLL is divided by a programmable divider 2 and compared with a reference frequency fR in phase through a phase detector 3. Then the phase difference detection voltage produced from the phase difference is fed back to the VCO1, and the frequency of the divider 2 is locked at the frequency fR. The digital code of a frequency setter 4 which controls the divider 2 is branched and converted into an analog form by a D/A converter 7 to be applied to an analog oscillator 5 outside the PLL. While an unlocked signal SU of the detector 3 is utilized to switch the oscillation output based on the VCO1 in the PLL is changed to an oscillation output based on the oscillator 5 by a switch 9 during the generating period of the signal SU. Thus the oscillation frequency of a PLL oscillator is stabilized.
申请公布号 JPS59114926(A) 申请公布日期 1984.07.03
申请号 JP19820224200 申请日期 1982.12.21
申请人 YAESU MUSEN KK 发明人 OGAWA NOBUO
分类号 H03L7/18;H03L7/187;H03L7/189 主分类号 H03L7/18
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