Microprocessor controlled communications controller having a stretched clock cycle

摘要

A communications controller of a data processing system uses a microprocessor to control communication operations. Apparatus in the controller stretches the microprocessor clock cycle signals for selected operations to allow the microprocessor speed to match the speed of the logic performing the selected operation. The apparatus includes a counter which is freerunning for the stretched cycle and reset on a predetermined cycle for the "no stretch" cycle. A decoder coupled to the counter conditions logic gates to generate the microprocessor clock cycle signals.