| 摘要 |
PURPOSE:To simplify the constitution and thus obtain a semiconductor memory whose manufacturing process is short and which actions stably by using a word line at a ground potential as a cell pair pole. CONSTITUTION:Data lines D and D' are connected to the drains of MISFET's Q3 and Q4 having gate electrodes connected to the word line WL1, the sources of these FET's are connected to data accumulated capacitors C3 and C4, and the pair poles of the C3 and C4 are connected to the other word line WL2 adjacent to the word line WL1. The word line WL1 is kept at a positive potential, and then ''1'' is written by giving a power source potential VCC to the line D and a ground potential to the line D'. At this time, the word line WL2 is kept at the ground potential. Next, the word line WL1 is turned to the ground potential, a terminal phi2 is turned to a positive potential, and the data lines D and D' are balanced by means of a balancing transistor QB, resulting in data holding state. The potential of the data lines D and D becomes approx. 1/2VCC. Then, when it is in a readout cycle, a positive potential is given again to the word line WL1, thus reading cell information out to the data lines D and D'. |
