| 摘要 |
PURPOSE:To reduce the short-circuit current in an output buffer to stabilize the operation, by providing two buffer amplifying parts and controlling the operation of one buffer amplifying part in accordance with an output enable signal and grasping the change of an address signal to generate its delay signal. CONSTITUTION:Two buffer amplifying parts 10A and 10B are provided, and respective input terminals and output terminals are connected commonly. A control signal A is supplied to gates of MOSFETs 13A and 17A, and a control signal A' is supplied to gates of MOSFETs 16A and 20A respectively. A control signal B is supplied to gates of MOSFETs 13B and 17B, and a control signal B' is supplied to gates of MOSFETs 16B and 20B respectively. In case that an output buffer 5 and a CPU generates a short-circuit through a bus line, the time when a conventional excessive short-circuit current is flowed is very shorter because the buffer amplifying part 10B controlled by control signals B and B' is operated only for a prescribed time after the change of the address signal. |
