| 摘要 |
PURPOSE:To set the priority among a data input, set input, and reset input optionally without increasing the number of transistors (TR) by altering the constitution of a gate which inputs the set signal and that of a gate which inputs the reset signal. CONSTITUTION:A clocked inverter G8 receives the data input DA and an NOR gate G9 inputs the reset input RE and the output of the clocked inverter G8. A clocked NOR gate G10 inputs the set input SE and the output of the NOR gate G9, and its output is connected to the output of the clocked inverter G8. The clocked inverter G8 and clocked NOR gate G10 operate alternately by a latch pulse LA and its inverted pulse LA'. Consequently, the priority of the output Q is in the order of the reset input RE, data input DA, and set input SE. Further, this circuit is realized by using a CMOS circuit, reducing TRs. |
