发明名称 |
TEST APPARATUS FOR INTEGRATED CIRCUIT DEVICE |
摘要 |
A test system having improved means for reducing driver switching (delta I) noise. The test system employs a tester connected to and electrically testing an integrated circuit device, such as a logic chip. The integrated circuit device has a plurality of input terminals (R5-R54) for receiving an electrical test pattern from the tester. The integrated circuit device also includes a plurality of output driver circuits (D2-D1O2) having outputs connected to the tester. The test system is characterized in that said integrated circuit device includes a driver sequencing circuit (L1-L1O) responsive to at least one control signal (R1-R4) from said tester to sequentially condition said driver circuits for possible switching, whereby delta I noise is reduced during testing. |
申请公布号 |
JPS6291873(A) |
申请公布日期 |
1987.04.27 |
申请号 |
JP19860180262 |
申请日期 |
1986.08.01 |
申请人 |
INTERNATL BUSINESS MACH CORP <IBM> |
发明人 |
EBUAN EZURA DEBITSUDOSON;DEEBITSUDO ARAN KIISURINGU |
分类号 |
H01L21/66;G01R31/28;G01R31/316;G01R31/319;H01L21/822;H01L27/04 |
主分类号 |
H01L21/66 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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