| 摘要 |
PURPOSE:To improve the throughput capability of data transfer by actuating a receiving buffer memory as a ring buffer. CONSTITUTION:A high-order address latching part 2 specifies an address space which can not be specified by a DMA (direct memory access) controller. The high-order address is updated by a BCD counter 3 counted up by a BCRSTOP signal from the controller 7 and set in the high-order address of a buffer by a clear controlling part 6. Consequently, the buffer memory 9 is operated as a ring buffer. Since the memory 9 is operated as the ring buffer, an intermediate buffer for other output devices is unnecessary even if data received from a high- speed circuit is transferred by the DMA. In addition, an output operation to other devices can be started simultaneously with the completion of reception, so that the throughput capability of data transfer can be improved. |
