发明名称 CONTROLLING SYSTEM OF MULTIPROCESSOR SYSTEM
摘要 PURPOSE:To improve the reliability and response of a system by forming a conversion table to make a specified address from another processor unit correspond to an effective address in a rewritable memory area. CONSTITUTION:When the generation of an error is detected, a CPUm 11 rewrites data indicating a block address corresponding to the device in which the error has been generated to ''1'' in all bits on the basis of the address conversion table previously stored in a variable memory 16. When the CPU 31 receives a read command from a CPU 21 in an operation sensor 20 and is to read out the address conversion table, the invalidation of the contents of the block address can be immediately checked by the table itself. Since the conversion table is formed in the rewritable memory area, the invalidation of the contents stored in the effective address can be confirmed and the reliability and response of the system is improved.
申请公布号 JPS59112356(A) 申请公布日期 1984.06.28
申请号 JP19820223296 申请日期 1982.12.20
申请人 YAMATAKE HONEYWELL KK 发明人 ISHIKAWA TERUO;KUMETA YASUO;ONOKI SEIJI
分类号 G06F15/16;G06F15/167;G06F15/177 主分类号 G06F15/16
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